In recent years, there have been several efforts to commercialize adhesive flip chip technologies. In the course of these efforts, manufacturers have learned of numerous reliability and manufacturing barriers that inhibit the wide spread use of adhesive flip chip assemblies. Failures occur in adhesive flip chip assemblies on glass or ceramic substrates for a variety of reasons. Electrical connections in most adhesive flip chip technologies occur through compressed contact points between the chip and substrate. As used herein, "substrate" refers generally to any material on which a plurality of electrical conductors can be constructed, deposited, etc. This design requires that tensile stress in the adhesive create and maintain the electrical contact throughout the life of the assembly. Loss of electrical contact can occur, however, when the adhesive expands or swells in the Z-axis direction. Expansion or swelling in the Z-direction may occur due to thermal expansion or moisture absorption. Gross delamination and tensile stress cracking may occur in the adhesive when the bond stresses are excessive. These can also cause Z-direction movement.
Adhesive flip chip assemblies often use protruding solid metal bumps or (in the case of anisotropically conducting adhesives) metal-coated polymer or solid metal particles to electrically connect a chip to the substrate. The flip chip systems use these bumps or particles because the chip pad is typically recessed 1 .mu.m or more beneath the chip passivation coating. Other chip or substrate topographies such as a warped or twisted substrate may preclude electrical contact without some sort of bump or particle between the chip and substrate. In the case of flip chip technologies that use anisotropically conducting adhesives, the particles are relatively small. Many particles have a diameter of less than approximately 10 .mu.m. The resulting bond line thickness for such a bump is also less than 10 .mu.m. This permits placing the bumps closely together without their touching one another. In these devices, reliable Z-axis connectivity occurs without undesirable lateral connections. High tensile stresses arise in these devices, however, particularly at the corners of the chip due to the thin adhesive bond line.
Flip chip assemblies that use solid metal bumps have an advantage of permitting bump height adjustments that optimize the bond line thickness to produce optimal stress levels. An example of a solid metal bumping technique appears in U.S. Pat. No. 4,693,770, entitled "Method of Bonding Semiconductor Devices Together," by K. Hatada, issued on Sep. 15, 1987, and assigned to Matsushita Electric Industrial Company, Limited (hereinafter Hatada). Hatada uses a solid gold bump to form the electrical connection from a die to a substrate. This is typical of LCD applications. A major problem with the device of Hatada, however, is that it is prone to fail due to adhesive creep-relaxation. But this is not the only problem with, solid metal bump configurations.
The coefficient of thermal expansion (CTE) of a solid metal bump is typically much lower than that of the adhesive that holds the flip chip device in contact with the substrate. As the flip chip increases in temperature, therefore, the adhesive expands faster than does the bump. This causes the flip chip to separate from the substrate. This thermal expansion, consequently, opens the circuit between the flip chip and the substrate.
Because of these issues, adhesive flip chip assemblies that use solid metal bumps require adhesives that possess extraordinary mechanical properties. The adhesives must have a low CTE and moisture absorptivity. In addition, the adhesive glass transition temperature, storage modulus, tensile and adhesion strengths must be high. Few adhesives have these properties. Those that do generally have manufacturing problems such as having short pot lives, lacking reworkability, producing residual ionics, and requiring long cure times.
Yet another limitation of existing flip chip bonding techniques relates to the point in the fabrication process at which bonding occurs. Most manufacturers of multi-chip electronic assemblies do not produce all of the integrated circuit die chips in their designs. Instead, they frequently purchase integrated circuit dies from various manufacturers who may not offer a flip chip bumping process. Often, these advanced chip manufacturers are very protective of any information that could be used by competitors or customers to deduce the cost of producing the chips. For this reason, they often refuse to supply integrated circuit chips in wafer form. This is because the complete wafers will indicate the integrated circuit yield from the wafers. The electrical yield of good chips per wafer is a primary cost driver. A competitor's knowledge of this cost information, therefore, can be detrimental to the business interests of the manufacturer. The inability to post-process flip chip devices on whole wafers to form these bumps limits the utility of flip-chip technology in multi-chip modules.
Consequently, the related art does not teach how to form a flip chip bump that overcomes the reliability and manufacturing barriers associated with making and using known electrically connective bumps.
The related art does not teach a method for forming connection bumps for adhesive flip chip assemblies that yields a bump that avoids tensile stress cracking, gross delamination, and loss of electrical contact problems of known adhesive flip chip assembly bumps. There is no teaching of an adhesive flip chip assembly bumping technology that ensures reliable Z-axis conductivity, and that overcomes the CTE-related problems of known adhesive flip chip assembly bumps.
There is no flip chip bump forming process that eliminates the need for adhesives that have the extraordinary mechanical properties of low CTE and moisture absorption together with a high glass transition temperature, storage modulus, and tensile and adhesion strength. The related art, furthermore, does not teach a method to connect bumps for adhesive flip chip assemblies that makes unnecessary special preparation of the assembly die.